On the error floor of the code-candidate for CCSDS standard

Luiza R. Medova, Pavel S. Rybin, Ivan V. Filatov

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper we propose a simulation system for LDPC codes implemented on a field-programmable gate array device. The presented system includes an LDPC encoder, Gaussian noise generator and an LDPC decoder. An LDPC encoder and decoder are fully flexible and support different constructions of LDPC codes. It makes possible to obtain performance curves of a large number of LDPC codes and analyse their properties. We have found that the LDPC code proposed in [1] has an error floor higher than the LDPC code proposed by the experimental specification CCSDS 231.1-O-l. We have evaluated the performance of 2250 (128, 256) LDPC codes with our simulation system and have found an LDPC code that outperforms the LDPC code from the experimental specification CCSDS 231.1-O-l.

Original languageEnglish
Title of host publication2019 International Conference on Engineering and Telecommunication, EnT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728135649
DOIs
Publication statusPublished - Nov 2019
Externally publishedYes
Event2019 International Conference on Engineering and Telecommunication, EnT 2019 - Dolgoprudny, Russian Federation
Duration: 20 Nov 201921 Nov 2019

Publication series

Name2019 International Conference on Engineering and Telecommunication, EnT 2019

Conference

Conference2019 International Conference on Engineering and Telecommunication, EnT 2019
Country/TerritoryRussian Federation
CityDolgoprudny
Period20/11/1921/11/19

Keywords

  • Bit-error rate (BER)
  • Experimental specification CCSDS
  • Fieldprogrammable gate array(FPGA)
  • Low-density parity check codes(LDPC)

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